1. Field of the Invention
The present invention relates to semiconductor devices such as integrated circuits and manufacturing method thereof. More specifically, it relates to an improved semiconductor wafer and device structure, and improvement of the manufacturing method thereof.
2. Description of the Background Art
Recently, the degree of integration of semiconductor integrated circuits has been much improved. As the degree of integration increases, the diameter of contact holes is made smaller, and impurity regions are formed shallower. Further, as the number of interconnection layers increase and provided in the form of multiple layers, inter-insulating layers insulating the interconnection layers from each other are stacked thick one after another. Consequently, the aspect ratio (depth/diameter) of the contact hole is increased.
Conventionally, an interconnection layer of aluminum.cndot.silicon (AlSi) or the like has been deposited by sputtering. However, because of directivity of plasma, a contact hole can not be covered by a film of uniform thickness by sputtering. Especially at sidewall portions and bottom portion of the contact hole, the interconnection layer becomes thin. Therefore, if the sidewall portion of the contact hole becomes steep, the interconnection layer is disconnected at the sidewall portion and the bottom portion.
In order to avoid the above described problem, recently a tungsten (W) plug utilizing CVD (Chemical Vapor Deposition) method has been developed. Reduction of tungsten hexafluoride (WF.sub.6) using hydrogen (H.sub.2) or silane (SiH.sub.4) have been known as methods for forming a tungsten thin film by using the CVD method. Respective reaction formulas for reduction of WF.sub.6 are as follows: EQU WF.sub.6 (g)+3H.sub.2 (g).fwdarw.W(s)+6HF(g) EQU 2WF.sub.6 (g)+3SiH.sub.4 (g).fwdarw.2W(s)+3SiF.sub.4 (g)+6H.sub.2 (g)
where (g) and (s) denote gas phase and solid phase, respectively.
The CVD-tungsten plug forming technique includes selective tungsten formation and etchback tungsten plug formation. Selective tungsten formation refers to a technique in which tungsten is grown or applied only in the contact hole, and for this reason, it is regarded as an ideal technique of filling. However, it has not yet been practically utilized because of the following reasons.
One reason is that the growth or application of tungsten in selective tungsten formation is sensitive to the surface condition. In selective tungsten formation, since growth of tungsten is sensitive to the surface condition, the growth reaction of tungsten differs dependent on underlayers. More specifically, when contact holes are formed not only on n type and p type impurity layers but also on underlayers such as n type and p type polysilicon (poly-Si) layer, tungsten polycide (WSi.sub.x /poly-Si) layer and titanium silicide (TiSi.sub.2) layer, it is difficult to uniformly fill all these contact holes formed on different underlayers. In addition, the depth of a contact hole with the silicon substrate being the underlying layer is different from the depth of a contact hole with a polysilicon layer being the underlying layer because of the thickness of polysilicon layer stacked on the substrate, and hence it is impossible to uniformly fill these contact holes.
Secondary, growth of tungsten is also sensitive to the surface condition of the insulating film in selective tungsten formation. More specifically, if there is a little residue or damage of the preceding steps left on the insulating film, such portion becomes a nuclear formation site, on which tungsten grows and will adhere. In this manner, a phenomenon of "lost selectivity" occurs and tungsten grows and remains not only in the contact holes but also on the insulating film.
From these reasons, selective tungsten formation is not practical.
Etchback tungsten plug formation refers to a technique in which a barrier metal such as titanium nitride (TiN) or titanium tungsten (TiW) is formed as a glue layer. A tungsten film is deposited entirely over the wafer and the tungsten is etched back entirely to leave tungsten plugs in contact holes. Compared with the aforementioned selective tungsten formation, the etchback tungsten plug formation is relatively easy, and practical application is expected. A conventional semiconductor device manufactured by using the etchback tungsten plug formation and manufacturing method thereof will be described in the following.
First, the structure of the conventional semiconductor device will be described.
FIG. 29 is a plan view schematically showing a conventional wafer. FIG. 30 is an enlarged plan view showing a portion B of FIG. 29. Referring to these figures, a plurality of device regions 260 are formed on the wafer 300. Device regions 260 are manufactured through etchback tungsten plug process. Dicing line portions 250 at which device regions are not formed exist between device regions 260. Alignment marks 220 are formed on dicing line portion 250. Alignment mark 220 is a projecting mark. Dicing line portion 250 is the region which is cut when wafer 300 is divided into chips, and it is cut along the line j--j, for example.
FIG. 31 is a partial cross section taken along the line n--n of FIG. 30, and FIG. 32 is a partial cross section taken along the line o--o of FIG. 30.
FIG. 31 shows a cross section of a portion where the alignment mark is not formed on the dicing line. Before cutting at dicing, dicing line portion 250 exists between device forming regions 260. As to the device forming region 260, an oxide film 203 for isolating element is formed on the surface of a semiconductor substrate 202. Between the oxide films 203, an MOS transistor 230 is formed. The MOS transistor 230 includes a gate electrode 204, a gate oxide film 205 and an impurity diffused region 206. An insulating layer 207 is formed on the surface of semiconductor substrate 202 in the device forming region 260. Insulating layer 207 has an opening 252 above the impurity diffused region 206. The surface of a portion of impurity diffused region 206 is exposed through this opening 252. A barrier metal 208 is formed thin in the periphery of the insulating layer 207, and at the sidewall portions and the bottom portion of the openings 252. The barrier metal 208 is formed of TIN/Ti. The opening 252 of insulating layer 207 is filled with a tungsten plug 201b. On the surface of insulating layer 207 and on tungsten plug 201, a first aluminum interconnection layer 209 is formed. The first aluminum interconnection layer 209 is electrically connected to impurity diffused region 206 through tungsten plug 201b. An interlayer insulating film 210 is formed on the surface of insulating layer 207 on which the first aluminum interconnection layer 209 is formed. A through hole 253 is provided in interlayer insulating film 210 on the first aluminum interconnection layer 209. A portion of the surface of the first aluminum interconnection layer 209 is exposed through this through hole 253. On the interlayer insulating film 210, a second aluminum interconnection layer 211 is formed. The second aluminum interconnection layer 211 is electrically connected to the first aluminum interconnection layer 209 through the through hole 253 of the interlayer insulating film 210. A passivation film 212 is formed to cover the surface of the second aluminum interconnection layer 211. The passivation film 212 has an opening. Through this opening, a portion of the surface of the second aluminum interconnection layer 212 is exposed, thus forming a bonding pad portion 213.
As to the dicing line portion 250, there is nothing formed on the surface of semiconductor substrate 202, and the surface of semiconductor substrate 202 is made rough because of etchback carried out to form the tungsten plug 201b. For simplicity, part of the dicing line portion 250 is not shown in the figure.
FIG. 32 is a cross section of a portion where an alignment mark is formed at the dicing line portion. Before cutting at dicing, dicing line portion 250 exists between device forming regions 260. The structure of the device forming region 260 is the same as that of FIG. 31 but with an alignment mark. A plurality of projecting alignment marks 220 are formed at dicing line portion 250. The surface of semiconductor substrate 202 where alignment mark 220 is not formed is made rough because of etchback for forming tungsten plug 201b. For simplicity, only a part of dicing line portion 250 is shown.
The conventional semiconductor device is structured as described above.
A method of manufacturing the conventional semiconductor device will be described in the following with reference to respective cross sections taken along the lines n--n and o--o of FIG. 30.
FIGS. 33 to 40 are cross sections taken along the line n--n of FIG. 30 showing, in order, the method of manufacturing the conventional semiconductor device. FIGS. 41 to 48 are cross sections taken along the line o--o of FIG. 30 showing, in order, the method of manufacturing the conventional semiconductor device.
Referring to FIGS. 33 and 41, an oxide film 203 for isolating elements is formed on semiconductor substrate 202. A MOS transistor 230 including a gate electrode 204, a gate oxide film 205 and an impurity diffused region 206 is formed at a region between oxide films 203. On the surface of semiconductor substrate 202, an insulating layer 207 is formed. A contact hole 252 is formed in the insulating layer 207 above impurity diffused region 206 by etching. Insulating layer 207 is also removed by etching in the region of dicing line portion 250. Referring particularly to FIG. 41, when insulating layer 207 is selectively removed from the region of dicing line portion 250, a plurality of alignment marks 220 are formed.
Referring to FIGS. 34 and 42, a barrier metal of TiN/Ti is formed by sputtering on the surface of semiconductor substrate 202.
Referring to FIGS. 35 and 43, a tungsten layer 201 is deposited by CVD method on the surface of semiconductor substrate 202. Thus, contact hole 252 is filled with a tungsten layer 201.
Referring to FIGS. 36 and 44, the entire surface of the deposited tungsten layer 201 is etched back. Thus a tungsten plug 201b is provided. By this etchback, the surface of semiconductor substrate 202 is made rough at the dicing line portion 250. Tungsten layer 201a is left as residue in the periphery of insulating layer 207. Referring particularly to FIG. 44, tungsten layer 201a is also left as residue in the vicinity of alignment mark 220. Referring to FIGS. 37 and 45, a first aluminum layer is formed on the entire surface of semiconductor substrate 202. The aluminum layer is etched and an aluminum interconnection layer 209 is formed. The first aluminum interconnection layer 209 is left on tungsten plug 201b. Referring particularly to FIG. 45, the first aluminum interconnection layer 209 is left also on alignment mark 220.
Referring to FIGS. 38 and 46, an insulating layer is formed on the entire surface of semiconductor substrate 202. The insulating layer is etched and an interlayer insulating film 210 is formed. Interlayer insulating film 210 is left only on the surface of insulating layer 207. Interlayer insulating film 210 on a part of the surface of the first aluminum interconnection layer 209 is also removed by etching. Consequently, a through hole 253 is formed in interlayer insulating film 210, and a portion of the surface of the first aluminum interconnection layer 209 is exposed. Referring particularly to FIG. 46, interlayer insulating film 210 is also left on alignment mark 220.
Referring to FIGS. 39 and 47, a second aluminum layer is formed on the entire surface of semiconductor substrate 202. The second aluminum layer is etched and a second aluminum interconnection layer 211 is formed. The second aluminum interconnection layer 211 is left only on insulating layer 207. Referring especially to FIG. 47, the second aluminum interconnection layer 211 is left also on alignment mark 220.
Referring to FIGS. 40 and 48, a passivation layer is formed on the entire surface of semiconductor substrate 202. The passivation layer is etched and a passivation film 212 is formed. By this etching, passivation film 212 is left to cover device forming portions 260. The passivation film 212 is also removed by etching from a portion of the surface of the second aluminum interconnection layer 211. Consequently, an opening is formed in passivation film 212, and a portion of the surface of second aluminum interconnection layer 211 is exposed. This exposed portion of the second aluminum interconnection layer 211 will be the bonding pad portion 213. Referring particularly to FIG. 48, passivation film 212 is also left on alignment mark 220.
The conventional semiconductor device is manufactured in the above described manner.
In the above described conventional semiconductor device, steps generated between the device forming region 260 and the dicing line portion 250 and steps generated by alignment marks can not be avoided as shown in FIGS. 31 and 32. Disadvantages derived from these steps will be described in the following.
FIG. 49 is a cross sectional view showing a step of forming tungsten plugs in a plurality of contact holes having different diameters. Referring to FIG. 49(a), contact hole H1 has the largest diameter, a contact hole H2 has smaller diameter, and a contact hole H3 has the smallest diameter. Referring to FIG. 49(b), a tungsten layer 201 is deposited on the entire surface. Referring to FIG. 49(c), the entire surface of tungsten layer 201 is etched back. Thus, a tungsten plug 201b is formed in the contact hole H3 having the smallest diameter. However, contact holes H2 and H1 having larger diameters than contact hole H3, filling of tungsten layer 201 is not sufficient, to fill holes H1 and H2 and therefore the substrate surface within H1 and H2 is made rough by etchback. This is because the thickness of tungsten layer 201 shown in the figure is too thin to fill contact holes H2 and H1. If the diameter is relatively near the diameter of contact hole H3 (for example, contact hole H2), the diameter can be adjusted to be the same as that of contact hole H3 by some change in design. Therefore, contact hole H2 can be fully filled, preventing roughness at the substrate surface. However, if the diameter is as large as that of contact hole H1, it is impossible to make small the diameter at the step of designing. It is impossible to fill the hole H1 by making the tungsten layer thicker. In a conventional semiconductor device, the portion of the contact hole H1 corresponds to the step portion generated by the dicing line or the alignment mark which is inevitable as described above. Therefore, at the step portion caused by the dicing line or the alignment mark, the substrate surface is made rough because of the etchback carried out when tungsten plug is formed. Especially at the dicing line, alignment marks are formed as shown in FIG. 30. The influence of the roughness of the substrate surface at the dicing line and the alignment marks will be described.
Generally, alignment of respective layers is carried out by using alignment marks. The alignment is carried out by scanning depressed or projecting alignment marks using He--Ne laser beam (.lambda.=633 nm), and by recognizing the center of the pattern of the alignment marks in accordance with the intensity of the reflected light.
FIG. 50 shows cross sections of depressed (a) and projecting (b) alignment marks and alignment waveforms when substrate surface is not made rough. FIG. 51 shows cross sections of depressed (a) and projecting (b) alignment marks and alignment waveforms when substrate surface is made rough.
Referring to FIG. 50, when an aluminum interconnection layer is provided on contact holes without using the tungsten plug process, the step of etchback of the tungsten layer is not carried out. Therefore, the substrate surface is not made rough. Consequently, both depressed (a) and projecting (b) alignment marks exhibit superior alignment waveforms. This enables recognition of the center of the alignment mark pattern.
When tungsten plug process is employed, referring to FIG. 51, the substrate surface is made rough because of the step of etching back the tungsten layer. The alignment waveforms are disturbed because of the surface roughness. If the disturbance of the alignment waveforms is as small as shown in (a) exhibited by the depressed alignment marks, the center of the pattern can be recognized. Therefore it can be used. However, the waveforms are disturbed much when projecting alignment marks (b) are used, that it becomes difficult to recognize the center of the pattern.
As described above, the etchback tungsten plug formation has the problem of surface roughness which in turn causes decrease in alignment precision.
A method has been proposed to solve the above problem, in which an insulating film is left on the entire surface of the dicing lines. This method will be described in the following.
FIG. 52 is an enlarged plan view corresponding to the portion B of FIG. 29. An insulating film is left on the substrate at dicing line portion 350. A plurality of alignment marks 320 are formed at dicing line portion 350. Alignment marks 320 are depressed type marks. The dicing line portion 350 is a region cut during dicing, and it is cut along the line k--k, for example.
FIG. 53 is a cross section taken along the line p--p of FIG. 52, and FIG. 54 is a cross section taken along the line q--q of FIG. 52. The same portions as in FIG. 31 and 32 are denoted by the same or corresponding reference characters. Referring to these figures, an insulating layer 307 is left on a semiconductor substrate 302. Therefore, the surface of semiconductor substrate 302 is not made rough even by the etchback for forming tungsten plugs. A plurality of depressed type alignment marks 320 are formed on the insulating layer 307. Even if etchback for forming tungsten plugs is carried out as shown in FIG. 51(a), the precision in alignment is not very much affected when depressed type alignment marks are used.
In this manner, by leaving an insulating film on the substrate at the dicing line portion, decrease of the alignment precision can be prevented. However, if the insulating layer is left as the dicing line portion as described above, the following problem arises when dicing is done along the line k--k of FIG. 52.
FIG. 55 is a cross section taken along the line p--p of FIG. 52 showing the manner of dicing along the line k--k of FIG. 52. Referring to FIG. 55, the insulating layer 307 and semiconductor substrate 302 at the dicing line are cut by a blade 340 of a dicer. However, during dicing, cracks are generated in insulating layer 307 and in semiconductor substrate 302. The cracks extend in insulating layer 307 to reach interconnection layer 315 of the device forming region 360 formed in the insulating layer 307. This causes short circuits between layers and decreases reliability.
Now, Japanese Patent Laying-Open No. 2-211652 discloses a structure of a semiconductor device which will be described in the following.
FIG. 56 is a cross sectional view showing schematically the structure of the semiconductor device disclosed in the above mentioned prior art. FIG. 56 shows a state before dicing the chip from the wafer, and there is a dicing line portion 450 which is cut during dicing, between device forming portions 460. An oxide film 403 for isolating elements is formed on the surface of the semiconductor substrate 402. An insulating layer 407 is formed on the surface of semiconductor substrate 402. The insulating layer 407 has an opening 451 in dicing line portion 450. Through this opening 451, a portion of the surface of semiconductor substrate 402 is exposed. At dicing line portion 450, a tungsten interconnection layer 401 is formed on insulating layer 407. The tungsten interconnection layer 401 covers insulating layer 407 at dicing line portion 450. Tungsten interconnection layer 401 fills the opening 451 in insulting layer 407. At device forming portions 460, an insulating film 423 is formed on insulating layer 407 and on tungsten interconnection layer 401.
The semiconductor device disclosed in the prior art is structured as described above. Referring now to FIG. 57. In this semiconductor device, the cracks in the insulating film 407 caused by dicing can be prevented from reaching other chips by the insulating layer 407 and tungsten plug 401 at the dicing line portion 450. However, the following problem still arises when the dicing line portion 450 is cut by the blade 440 of a dicer.
FIG. 58 is a perspective view showing the dicing line portion of the semiconductor device disclosed in the prior art after the cutting of the dicing line portion. Referring to FIG. 58, in the semiconductor device disclosed in the prior art, tungsten interconnection layer 401 is formed to cover the entire surface of insulating layer 407 at dicing line portion 450. Therefore, when it is cut, the tungsten interconnection layer 401 must be cut first, as shown in FIG. 57. By this cutting, pieces of tungsten interconnection layer 401 scatters and may possibly bridge bonding pads 413, as shown in FIG. 58. Cutting of the interconnection layer thus possibly causes a short-circuit between bonding pads. In addition, two layers, that is, tungsten interconnection layer 401 and insulating layer 407 must be cut. Therefore, if the tungsten interconnection layer 401 is formed of a material with high hardness, the blade 440 of the dicer wears, and the number of failure would be increased. In other words, this prior art has a problem of short life of the blade 440 of the dicer.